component test1
	port (
		a: in STD_LOGIC;
		clk: in STD_LOGIC;
		enable: in STD_LOGIC;
		reset: in STD_LOGIC;
		z: out STD_LOGIC);
end component;


instance_name : test1
( a => ,
 clk => ,
 enable => ,
 reset => ,
 z => );
